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Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is
provided by the external address. The burst address counter wraps around to its initial state upon completion.
The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected.
And when this pin is high, Interleaved burst sequence is selected.
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Ready/Busy status is indicated using bit 7 0f the status register. If bit 7 is a l, then the
device is not busy and is ready to accept the next command. If bit 7 is a 0, then the
device is in a busy state. The user can continuously poll bit 7 0f the status register by
stopping SCK at a low level once bit 7 has been output. The status of bit 7 will continue
to be output on the SO pin, and once the device is no longer busy, the state of SO will
change from o t0 1. There are eight operations which can cause the device to be in a
busy state: Main Memory Page to Buffer Transfer, Main Memory Page to Buer Com-
pare, Buffer to Main Memory Page Program with Built-in Erase, Buffer to Main Memory
Page Program without Built-in Erase, Page Erase, Block Erase, Main Memory Page
Program, and Auto Page Rewrite.
2SK1625S datasheet

Collector-Emitter Saturation Voltage VCE(sat) lC = 300A, VGE = 15V, Ti = 25YC - 2.4 3.0 Volts
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2SK1625S pdf

Emitter-Collector Voltage VEC IE = 100A, VGE = OV - 3.8 Volts