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The imager is structured in a serial-parallel-serialconfigu ration
so charge packets (imaging data) in the vertical (parallel)
registers can be shifted either up or down to two identical
horizontal (serial) shift registers. One is at the top and another
is at the bottom of the array. Three-phase clocks are needed
to drive both vertical and horizontal shift registers.
AD642LHC   seller 


INPUT PULSE REQUIREMENTS

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tTLH


tTHL

74F

3.OV

1.5V

1MHz

500ns

2.5ns

2.5ns


AD642LHC   datasheet 

4 8 12 16 20 0.6 1.0 1.4 1.8 2.2 2.6 3.0 10-i 100 10i 102
AD642LHC   price 


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AD642LHC   pdf 

' On-chip op amplifier for caching applications reduces
extemal components.

' Reduced switching noise with silicon gate CMOS
processor.

' All controls performed using serial data input (C;B).
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