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Figure 4A shows the timing of the horizontal three-phase

clocks, su m ming well clock, reset clock, and external clamping
and sampling clocks. To achieve high charge transfer effi-

ciency and high fullwell capacity, serial clocks must overlap by
more than l ys. In addition, the rise and fall times of the three-
phase clocks may be more than 300 ns to prevent possible
injection of spurious charge into the CCD channei. After the
three-phase clock transitions, the clocks are held steady to
provide a quiet period for signal readout. During this quiet
period, the output amplifier is clamped and the signal charge
in the summing wellis transferred into the output sensing node.
The output signal is then sampled and the sensing node is
reset.
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