Stock Map: 1   2   3   4   5   6   7   8   9   10   11   12   13   14   15  
1,EPS464LC44-20 are hot selling, Following list are globle excellent suppliers of EPS464LC44-20, If you want to purchase EPS464LC44-20, you can contact the suppliers of EPS464LC44-20 by email，telephone or leave a message for them.
2,Enter the right button for EPS464LC44-20 DATASHEET Download of EPS464LC44-20, free for datasheet of EPS464LC44-20 

EPS464LC44-20,Top sales EPS464LC44-20,EPS464LC44-20 DATASHEET
EPS464LC44-20  Top sales 



PARAMETER


TEST b


2


DESCRIPTION1


-60


UNITS

COND.


MIN

MAX

tpdl
A
1
Data Propagation Delay, 4PT bypass, ORP bypass
20
ns

tpd2
A
2
Data Propagation Delay, Worst Case Path
25
ns


fmax (lnt.)
A
3
Clock Frequency with Internal Feedback3
60
MHz

fmax (Ext.)
4

Clock Frequency with External FeedbackijI
\tsu2 + tcol
38
MHz

fmax (Tog.)
5
Clock Frequency, Max Toggle4
83
MHz

tsul
6
GLB Reg. Setup Time before Clock, 4PT bypass
9
ns

tcol
A
7
GLB Reg. Clock to Output Delay, ORP bypass
13
ns

thl
8
GLB Reg. Hold Time after Clock, 4 PT bypass
0
ns

tsu2
9
GLB Reg. Setup Time before Clock
13
ns

tc02
10
GLB Reg. Clock to Output Delay
16
ns

th2
1 1
GLB Reg. Hold Time after Clock
0
ns

trl
A
12
Ext. Reset Pin to Output Delay
22.5
ns

trwl
13
Ext. Reset Pulse Duration
13
ns

ten
B
14
Input to Output Enable
24
ns

tdis
c
15
Input to Output Disable
24
ns

twh
16
Ext. Sync. Clock Pulse Duration, High
6
ns

twl
17
Ext. Sync. Clock Pulse Duration, Low
6
ns

tsu5
18
I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3)
2.5
ns

th5
19
I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
8.5
ns


EPS464LC44-20   seller 


05/13/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 A Tel: 408.263.3214 A Fax: 408.263.7846 A www.calmicro.com 7
EPS464LC44-20   datasheet 

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper lC Handling Procedures
Copyright 2003, Texas Instruments Incorporated
EPS464LC44-20   price 


Option
Conditions and notes

I Output high at reset

The four bits of ports 0, 1, 4, 5, or 8 are set in a group

I Output low at reset
The four bits of ports 0, 1, 4, 5, or 8 are set in a group


EPS464LC44-20   pdf 

Bypass Read Operation
Since write data is not fully written into the array on first write cycle, there is a need to sense the address in case a future read is to
be done from the location that has not been written yet. For this case, the address comparator check to see if the new read address
is the same as the contents of the stored write address Latch. If the contents match, the read data must be supplied from the stored
write data latch with standard read timing. If there is no match, the read data comes from the SRAM array. The bypassing of the
SRAM array occurs on a byte by byte basis. If one byte is written and the other bytes are not, read data from the last written will have
new byte data from the write data buffer and the other bytes from the SRAM array.
©© Copyright:-www.13ic.Com 2000-2010 Message at MSN:search_01@live.com
Service hot :(86)-0755-86525401 Fax:86-755-84521245