HD74ALVC16835TEL,Top sales HD74ALVC16835TEL,HD74ALVC16835TEL DATASHEET -ICSTOCK

PARAMETER	SYMBOL	CONDITIONS	MIN	TYP	MAX	UNITS
Output Voltage	VOUT	L,SD,CL, etc. connected	4 875	5 000	5 125	V
Maximum Input Voltage	VIN		10			V
Oscillation Start-up Voltage	VST	IOUT=lmA		0 80	0.90	V
Oscillation Hold Voltage	VHLD	IOUT=lmA	0.70			V
No-Load Input Current	llN	IOUT=OmA,(Notel)		5 3	10 6	A
Supply Current l (Note 2)	IDD1	VIN=VOUT X 0.95		47 8	95 7	A
Supply Current 2	IDD2	VIN=VOUT+0.5V		2 4	4 8	A
Lx Switch On-Resistance	RSWON	Same as IDDl, VLx=0.4V		2 8	4 3	Q
Lx Leakage Current	ILXL	No external components, VOUT=VLx=lOV			1 0	A
Duty Ratio	DTY	Same as IDD1 Measuring of Lx waveform	53	58	63	%
Maximum Oscation Frequency	MAXFosc	Same as IDDl, 58% duty.	131 75	155	178 25	kHz
Lx Limit Voltage	VLxLMT	Same as IDDl, Fosc>MAXFosc x 2	0 7		1 1	V
Efficiency	EFFI	L,SD,CL, etc. connected		85		%

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Parameter	Symbol	Test Conditions	Minimum	Typical	Maximum	Units
MIX 1900 (continued)
Output impedance		Set externally using defined circuit topology.		400
LO input port impedance		Internal match. External AC coupled		50
LO input port load isolation		Active/standby transition	-20			dB
Required LO level			-13	-10	-5	dBm
LO to RF port isolation		Referenced to LO input pin		30		dB
LO to IF port isolation		Referenced to LO input pin		20		dB
MIX-2
Input frequency range			120		180	MHz
Output frequency				450		kHz
Power gain		-40 to +85 1C 15 dB of power gain = 22 dB of Volt gain	14	15	16	dB
Noise figure		15 t0 50 IC -40 to +85 lC		12	13 14	dB
Input impedance		Differential, possible to use single-ended also		400
Output PldB				-8		dBm
Output IP3		15 t0 50 YC -40 to +85 IC	1 0	2		dBm
Required LO level for external source		High input impedance. In place of the internal VC0		300		mVp-p
LO leakage at RF port		Assuming 50 I calculation or match			-40	dBm
LO leakage at IF port		Assuming 50 I calculation or match			-30	dBm
Output impedance		Single-ended	1.8k	2k	2.2k
VGA 450
Frequency range			300	450	500	kHz
Dynamic range				70		dB
Maximum voltage gain Maximum power gain				54 70		dB dB
Input noise figure, maximum gain Input noise figure, minimum gain				43	15	dB
Input PldB @ Gain = 0 dB				-20		dBm
Output IP3 @ Gain = 0 dB		IP3 will remain constant over the entire gain range		-10		dBm
Input impedance		Differential		2k
Gain slope				45		dBN
VGA control		Analog control voltage	0 25		2 5	V

HD74ALVC16835TEL datasheet

ADVANTAGES
Space and weight savings
* Simple mounting
' Improved temperature and power
cycling
Reduced protection circuits
HD74ALVC16835TEL price

After conversion of all 8 channels the results are storaged
in the result RAM. After ending the conversion of channel 7
the output INT becomes active (low ). This output can be
used to trigger a microcontroller with interrupt or DMA
request.
HD74ALVC16835TEL pdf

Parameter	Symbol	Test Condition	Min	Typ.	Max	Unit
Vcc for Data Retention	VDR	CS>Vcc-0.2V	2 0		3 6	v
Data Retention Current	IDR	Vcc=3.OV, CS>Vcc-0.2V VIN>Vcc-0.2V or VIN10.2V			0 5	mA
Data Retention Current	IDR	Vcc=2.OV, CS>Vcc-0.2V VIN>Vcc-0.2V or VIN10.2V			0 4	mA
Data Retention Set-Up Time	tSDR	See Data Retention	O			ns
Recovery Time	tRDR	Wave form(below)	5			ms