HM5116100AS-6,Top sales HM5116100AS-6,HM5116100AS-6 DATASHEET

In addition to polynomial selection there are four other
capabilities provided for in the 74F402 ROM. The first is set
or clear selectability. The sixteen internal registers have the
capability to be either set or cleared when P is brought
LOW. This set or clear capability is done in four groups of 4
(see Table 2, PO-P3). The second ROM capability (Co) is in
determining the polarity of the check word. As is the case
with the Ethernet polynomial the check word can be
inverted when it is appended to the data stream or as is the
case with the other polynomials, the residue is appended
with no inversion. Thirdly, the ROM contains a bit (Ci)
which is used to select the RFB input instead of the SEI
input to be fed into the LSB. This is used when the polyno-
mial selected is actually a residue (least significant) stored
in the ROM which indicates whether the selected location

is a polynomial or a residue. If the latter, then it inhibits the
RFB input.

As mentioned previously, upon a successful data transmis-
sion, the CRC register has a zero residue. There is an
exception to this, however, with respect to the Ethernet
polynomial. This polynomial, upon a successful data trans-
mission, has a non-zero residue in the CRC register (C7 04
DD 7B)16. In order to provide a no-error indication, two
ROM locations have been preloaded with the residue so
that by selecting these locations and clocking the device
one additional time, after the last check bit has been
entered, will result in zeroing the CRC register. In this man-
ner a no-error indication is achieved.
HM5116100AS-6   pdf