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Absolute Maximum Ratings Thermallnformation
DC Supply Voltage, Vcc . . . . . . . . . . . -0.5V t0 7V Package Thermal Impedance, OJA (see Note l):
DC Input Diode Current, IIK E (PDIP) Package . . . . . . . . .670C/W
DC Output Diode Current, lOK NS (SOP) Package . . . . . . . . . . . . . . . .640C/W
For VO < -0.5V or VO > Vcc + 0.5V . . . . . . . . . . . . . .+20mA PW (TSSOP) Package . . . . . . . . . . . 1080C/W
DC Output Source or Sink Current per Output Pin, 10 Maximum Junction Temperature . . . . . . . . . . . . . . . . . 1500C
For VO > -0.5V or VO < Vcc + 0.5V . . . . . . . . . . . . . .+25mA Maximum Storage Temperature Range . . . . . . . . . .-650C t0 1500C
DC Vcc or Ground Current, ICC orIGND... ........ .+50mA Maximum Lead Temperature (Soldering 10s~ 3000C
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . ' ' ' ' ' ' . . . . . . . . . -550c t0 1250C
Supply Voltage Range, Vcc
HCT Types . . . . . . . . . . . .4.5V t0 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . OV to Vcc
Input Rise and Fall Time
CAUTiON: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating, and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications | | | | |
TE{
CONDI'
|
T
10NS
|
vcc |
250C
|
.400C T0 850C
|
.55aC T0 1250C
| | |
PARAMETER |
SYMBOL |
vI (V) |
lo (mA) |
(v) |
MIN |
TYP |
MAX |
MIN |
MAX |
MIN |
MAX |
UNITS |
HC TYPES |
High Level Input |
VIH | | |
2 |
1.5 | | |
1 5 | |
1 5 | |
V |
Voltage
|
4 5 |
3.15 | | |
3 15 | |
3 15 | |
V
|
6 |
4.2 | | |
4 2 | |
4 2 | |
V |
Low Level Input |
VIL | | |
2 | | |
0.5 | |
0.5 | |
0.5 |
V |
Voltage
|
4 5 | | |
1.35 | |
1 35 | |
1.35 |
V
|
6 | | |
1.8 | |
1.8 | |
1.8 |
V |
High Level Output |
VOH |
VIH or VIL |
-0.02 |
2 |
1.9 | | |
1 9 | |
1 9 | |
V |
Voltage |
-0.02 |
4 5 |
4.4 | | |
4 4 | |
4 4 | |
V |
CMOS Loads
|
-0.02 |
6 |
5.9 | | |
5 9 | |
5 9 | |
V |
High Level Output | | | | | | | | | |
V |
Voltage |
4 |
4 5 |
3.98 | | |
3 84 | |
3 7 | |
V |
TTL Loads
|
-5.2 |
6 |
5 48 | | |
5 34 | |
5 2 | |
V |
Low Level Output |
VOL |
VIH or VIL |
0 02 |
2 | | |
0.1 | |
0.1 | |
0.1 |
V |
Voltage |
0 02 |
4 5 | | |
0.1 | |
0.1 | |
0.1 |
V |
CMOS Loads
|
0 02 |
6 | | |
0.1 | |
0.1 | |
0.1 |
V |
Low Level Output | | | | | | | | | |
V |
Voltage |
4 |
4 5 | | |
0.26 | |
0 33 | |
0.4 |
V |
TTL Loads
|
5.2 |
6 | | |
0.26 | |
0 33 | |
0.4 |
V |
Input Leakage
Current |
lI
|
Vcc or
GND | |
6
| | |
+0 1
| |
+1
| |
±1
|
ccA
|
Quiescent Device
Current |
lcc
|
Vcc or
GND |
0
|
6
| | |
8
| |
80
| |
160
|
o:A
| | | | | | | | | | | | | | | | | |
K1872 seller
Dimensions |
Inches |
Mimeters |
N |
0 65 |
16 5 |
D |
0 49 |
12 5 |
Q |
1 04 |
26 5 |
R |
2 09 |
53 0 |
S |
0 08 |
2 0 |
T |
0 02 |
0 5 |
U |
2 13 |
54 0 |
V |
0 04 |
1 0 |
W |
0 03 |
0 8 |
x |
0 32 |
8 0 |
Y |
0 21 |
5 3 |
Z |
0 20 |
5 0 | | | |
K1872 datasheet -40 t0 125 IC Storage Temperature Tstg
K1872 price 12 AdldCes~dBeit 0(12C) / Control Port Chip Select (SPI) (lnput) - ADO is a chip address pin e; CS is the chip select signal for SPI format.
K1872 pdf
1 |
MARK |
10GWJ2C |
TYPE |
10GWJ2C48C, U10GWJ2C48C |
2 |
C |
3
|
Lot Number
Month (Starting from Alphabet A)
Year (Last Number of the Christian Era) | | | | | |
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