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Absolute Maximum Ratings Thermallnformation
DC Supply Voltage, Vcc . . . . . . . . . . . -0.5V t0 7V Thermal Resistance (Typical, Note l) OJA (oC/W)
DC Input Diode Current, IIK E (PDIP) Package . . . . . . . . 69
DC Output Diode Current, lOK Maximum Junction Temperature . . . . . . . . . . . . . . . . . 1500C
For VO < -0.5V or VO > Vcc + 0.5V . . . . . . . . . . . . . .+20mA Maximum Storage Temperature Range . . . . . . . . . .-650C t0 1500C
DC Drain Current, per Output, 10 Maximum Lead Temperature (Soldering 10s~ 3000C
For -0.5V < VO < Vcc + 0.5V. . . . . . . . . . . . . . . . . . . .+35mA (SOIC _ Lead Tips Only)
DC Output Source or Sink Current per Output Pin, 10
For VO > -0.5V or VO < Vcc + 0.5V . . . . . . . . . . . . . .+25mA
DC Vcc or Ground Current, ICC . . . . . . . . . . . . . . . . . . .+50mA
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . -550c t0 1250C
Supply Voltage Range, Vcc
HCT Types . . . . . . . . . . . .4.5V t0 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . OV to Vcc
Input Rise and Fall Time
CAUT10N: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications | | | | |
TEf
CONDI'
|
T
10NS
|
vcc |
250C
|
.400C T0 85aC
|
.55aC T0 1250C
| | |
PARAMETER |
SYMBOL |
vI (V) |
lo (mA) |
(v) |
MIN |
TYP |
MAX |
MIN |
MAX |
MIN |
MAX |
UNITS |
HC TYPES |
High Level Input |
VIH | | |
2 |
1.5 | | |
1 5 | |
1 5 | |
V |
Voltage |
4 5 |
3.15 | | |
3 15 | |
3 15 | |
V |
6 |
4.2 | | |
4 2 | |
4 2 | |
V |
Low Level Input |
VIL | | |
2 | | |
0.5 | |
0.5 | |
0.5 |
V |
Voltage |
4 5 | | |
1.35 | |
1 35 | |
1.35 |
V |
6 | | |
1.8 | |
1.8 | |
1.8 |
V |
High Level Output |
VOH |
VIH or VIL |
-0.02 |
2 |
1.9 | | |
1 9 | |
1 9 | |
V |
Voltage |
-0.02 |
4 5 |
4.4 | | |
4 4 | |
4 4 | |
V |
CMOS Loads
|
-0.02 |
6 |
5.9 | | |
5 9 | |
5 9 | |
V |
High Level Output | | | | | | | | | |
V |
Voltage |
6 |
4 5 |
3.98 | | |
3 84 | |
3 7 | |
V |
TTL Loads
|
-7.8 |
6 |
5 48 | | |
5 34 | |
5 2 | |
V |
Low Level Output |
VOL |
VIH or VIL |
0 02 |
2 | | |
0.1 | |
0.1 | |
0.1 |
V |
Voltage |
0 02 |
4 5 | | |
0.1 | |
0.1 | |
0.1 |
V |
CMOS Loads
|
0 02 |
6 | | |
0.1 | |
0.1 | |
0.1 |
V |
Low Level Output | | | | | | | | | |
V |
Voltage |
6 |
4 5 | | |
0.26 | |
0 33 | |
0.4 |
V |
TTL Loads
|
7.8 |
6 | | |
0.26 | |
0 33 | |
0.4 |
V |
Input Leakage
Current |
lI
|
Vcc or
GND | |
6
| | |
+0.1
| |
+1
| |
±1
|
| | | | | | | | | | | | | | | | | |
K9K8G08UOA-PCB0 seller
Dimensions |
Inches |
Mimeters |
A |
5.00 |
127.0 |
B |
4.33+0.01 |
110.0+0 2 |
c |
3.86 |
98.0 |
D |
2.20 |
56.0 |
E |
1.57 |
40O |
F |
1.12 |
28.5 |
G |
1.04 |
26.5 |
H |
1.01 |
25.6 |
J |
O98 |
25O | | | |
K9K8G08UOA-PCB0 datasheet | | | | | |
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K9K8G08UOA-PCB0 price ( S d Y J V ) 2 I N a ] 0 A A 0 0 3 S 3 A
K9K8G08UOA-PCB0 pdf
L:I DC bias must be provided for the RF, LO and IF
amplifiers in the converter. Rl sets the operating current for the last
stage of the LO amplifier and is chosen to optimize the mixer LO
drive level. Proper RF chokes and bypass capacitors are chosen for
proper amplifier biasing at the intended frequency of operation. The
"+5 V" dc bias should be supplied directly from a voltage regulator.
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