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The state machine in the MSTR_CON PAL device rep-
resents the heart of the bank interleaved memory de-
sign. It controls the main memory functions of both the
DRAM access and the refresh of the DRAMs, and also
provides decoding and timing for the ROM access. This
is done in a way that hides the refreshes so they do not
impact performance; forexample, DRAM refresh can be
performed while ROM is being accessed. Additionally,
state bits are shared between state machines so that ex-

tra flip-flops are not needed. For example, this sharing is
done for ROM access because a 3-cycle access on
ROM is needed at 30 MHz,while in 16 MHzonly 2 cycles
are needed. So a simple division by 2 needs to change
to a division by 3, which requires one more state bit.
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