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erate (CWG) must be held HIGH while the data is being
entered. After the last data bit is entered, the CWG is
brought LOW and the check bits are shifted out of the reg-
ister(s) and appended to the data bits (no external gating is
needed).

To check an incoming message for errors, both the data
and check bits are entered through the D Input with the
CWG Input held HIGH. The Error Output becomes valid
after the last check bit has been entered into the 'F402 by a
LOW-to-HIGH transition of CP, with the exception of the
Ethernet polynomial (see Applications paragraph). If no
detectable errors have occurred during the data transmis-
sion, the resultant internal register bits are all LOW and the
Error Output (ER) is HIGH. If a detectable error has
occurred, ER is LOW. ER remains valid until the next LOW-
to-HIGH transition of CP or until the device has been pre-
set or reset.
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