MM5675BJ,Top sales MM5675BJ,MM5675BJ DATASHEET -ICSTOCK

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Numb erOf Eq uaIAmplit ude Half C ycle Current Pulse s (N

Fig. 6 - Maximum Non-Repetitive Surge Current
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* VDD : 2.6V + O.1V, VDDQ : 2.6V + O.1V for DDR400

. Double-data-rate architecture; two data transfers per clock cycle

. Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16)
. Four banks operation

. Differential clock inputs(CK and CK)

. DLL aligns DQ and DQS transition with CK transition

. MRS cycle with address key programs

-. Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
. All inputs except data & DM are sampled at the positive going edge of the system clock(CK)

. Data l/0 transactions on both edges of data strobe

. Edge aligned data output, center aligned data input

. LDM,UDM for write masking only (x16)

. DM for write masking only (x4, x8)
. Auto & Self refresh

. 7.8us refresh interval(8K/64ms refresh)

. Maximum burst refresh cycle : 8

. 66pin TSOP II Pb-Free package
. .
MM5675BJ datasheet

Parameter	Symbol	Limit Values		Unit
Parameter	Symbol	min	max	Unit
Minimum time the bus must be free before a new transmission can start	tBUF	4 7		11S
Start condition hold time	HDSTA	4O		US
Clock low period	fLoW	47		Lis
Clock high period	'HIGH	4.0		Lis
Start condition set-up time, only valid for repeated start code	tSU;STA	47		¨S
Data set-up time	SUDAT	250		ns
Rise time of both the SDA and SCL line			1	Lis
Fall time of both the SDA and SCL line			300	Lis
Stop condition set-up time	'SUSPO	47		US

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DC Electrical Specifications (Continued)
				TE COND	ST TIONS			250C						400C TO +85aC				.55aC T0 1250C
	PARAMETER	SYMBOL		vI (V)	lo (mA)	vcc (v)		MIN		TYP		MAX		MIN		MAX		MIN	MAX	UNITS
	HCT TYPES
	High Level Input Voltage	VIH				4.5 to 5 5		2						2				2		V
	Low Level Input Voltage	VIL				4.5 to 5 5						0 8				0.8			0.8	V
	High Level Output Voltage CMOS Loads	VOH		VIH or VIL	-0.02	4 5		4 4						4.4				4.4		V
	High Level Output Voltage TTL Loads				4	4 5		3 98						3 84				3.7		V
	Low Level Output Voltage CMOS Loads	VOL		VIH or VIL	0.02	4 5						0 1				0.1			0.1	V
	Low Level Output Voltage TTL Loads				4	4 5						0 26				0 33			0.4	V
	Input Leakage Current	ll		Vcc to GND	0	5 5						+0.1				+1			+1
	Quiescent Device Current	lcc		Vcc or GND	O	5 5						8				80			160
	Additional Quiescent Device Current Per Input Pin: 1 Unit Load	C:lcc (Note 2)		Vcc -2.1		4.5 to 5 5				100		360				450			490	o:A
NOTES: 2. For dual-supply systems theoretical worst case (VI = 2.4V, Vcc = 5.5V) specification is l.8mA. HCT Input Loading Table
	INPUT		UNIT LOADS
	MR		1
	CP		0 60
	D		0 15
NOTE: Unit Load is Clcc limit specified in DC Electrical Specifications table, e.g. 360ccA max at 250C. Prerequisite For Switching Specifications
					TEST		vcC		250C						.400C T0 850C			.550C T0 1250C
	PARAMETER		SYMBOL		CONDITIONS		(v)		MIN		TYP		MAX		MIN		MAX	MIN	MAX	UNITS
	HC TYPES
	Clock Pulse Width		tw				2		80						100			120		ns
							4 5		16						20			24		ns
							6		14						17			20		ns
	MR Pulse Width		tw				2		80						100			120		ns
							4 5		16						20			24		ns
							6		14						17			20		ns

MM5675BJ pdf

SYMBOL	PARAMETER	CONDITIONS	MIN	TYP	MAX	UNIT
f	Frequency Range		330		400	MHz
Pout	Output Power	VDD=12.5V,VGG=3.5V, Pin=20mW	7			W
11T	Total Efficiency		40			%
2fo	2'd Harmonic	Pout=7W (VGG control),			-25	dBc
Pin	Input VSWR	VDD=12.5V, Pin=20mW			4:1
IGG	Gate Current	VDD=12.5V, Pin=20mW		1		mA
	Stability	VDD=7.2-15V, Pin=10-30mW, Pout<8W (VGG control), Load VSWR=4:1	No parasitic oscillation
	Load VSWR Tolerance	VDD=1 3.2V, Pin=20mW, Pout=7.OW (VGG control), Load VSWR=20:1	No degradation or destroy