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DV2, DVl, DVO - These three bits are used to turn the oscillator on or off and to reset the countdown
chain. A pattern of 010 is the only combination of bits that will turn the oscillator on and allow the RTC
to keep time. A pattern of 11X will enable the oscillator but holds the countdown chain in reset. The next
update will occur at 500 ms after a pattern of010 is written to DVO, DVl, and DV2.
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Parameter	Symbol	Limits	Unit
Total power dispation	PD	1 0	W/TOTAL
Range of strage temperature	Tstg	40+125	1c

S77M datasheet

Name	Function	Name	Function
CSl,CS2	Chip Select Inputs	Vcc	Power
OE	Output Enable Input	Vss	Ground
WE	Write Enable Input	UB	Upper Byte(l/09~16)
AoA19	Address Inputs	LB	Lower Byte(l/01~8)
l/0il/016	Data Inputs/Outputs	NC	No Connectioni)

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S77M pdf

The K9K'1208UOA is a 528Mbit(553,648,218 bit) memory organized as 131,072 rows(pages) by 528 columns. Spare sixteen col-
umns are located from column address of 512 t0 527. A 528-byte data register is connected to memory cell arrays accommodating
data transfer between the l/0 buffers and memory during page read and page program operations. The memory array is made up of
16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the
32 pages formed by two NAND structures, totaling 8,448 NAND structures of 16 cells. The array organization is shown in Figure 2.
The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The mem-
ory array consists of 4,096 separately erasable 16K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the
K9K1208UOA.